1. Field of the Invention
The present invention relates to a process for manufacturing a non-volatile semiconductor memory device. More particularly, the present invention relates to a process for manufacturing a non-volatile semiconductor memory device comprising memory cells having a tunnel dielectric film, a floating gate electrode, a control gate electrode and an interlayer capacitive film formed between the floating gate electrode and the control gate electrode.
2. Description of the Related Arts
With reference to FIG. 7 to FIG. 12(b), an explanation is given on a general process for manufacturing a non-volatile semiconductor memory device in which memory cells having a floating gate electrode and a control gate electrode are formed on a semiconductor substrate.
FIG. 7 is a plan view of a memory cell portion, in which the dotted line represents an interface between an active region and a device isolation region; CG represents a control gate electrode region; and FG represents a floating gate electrode region. FIGS. 8(a) to 12(b) show a prior art process for manufacturing a memory cell portion. In FIG. 8(a) to FIGS. 12(b), (a) represents an X-X' cross section of FIG. 7, and (b) represents a Y'-Y cross section of FIG. 7.
First, a device isolation region 22 comprising a silicon oxide film of 500 nm and an active region 23 are formed on a P-type semiconductor substrate 21 by LOCOS method. Thereafter, a tunnel oxide film 24 is formed to a thickness of about 10 nm on the active region 23 by thermal oxidation, and then a polysilicon film 25 doped with phosphorus as an impurity is deposited to a thickness of about 100 nm as a material for a floating gate electrode.
Subsequently, the polysilicon film 25 is patterned by reactive ion etching using, as a mask, a resist R11 patterned by means of photolithography so as to form the floating gate electrode, as shown in FIGS. 8(a) and 8(b).
After the resist R11 is removed, an ONO film (a three-layer film of first silicon oxide film 26 (SiO.sub.2)/silicon nitride film 27 (SiN)/second silicon oxide film 28 (SiO.sub.2)) is formed as an interlayer capacitive film between the floating gate electrode and the control gate electrode, as shown in FIGS. 9(a) and 9(b). Namely, a first silicon oxide film 26 is formed to a thickness of 8 nm on a surface of the floating gate electrode by thermal oxidation method; then a silicon nitride film 27 is formed to a thickness of 20 nm by CVD (Chemical Vapor Deposition) method; and further a second silicon oxide film 28 is formed to a thickness of 8 nm, successively. After the ONO film is formed, a polycide film 29 is deposited to a thickness of about 100 nm as a material for the control gate electrode.
Then, the polycide film 29 is patterned by reactive ion etching using, as a mask, a resist R22 patterned by means of photolithography so as to form the control gate electrode, as shown in FIGS. 10(a) and 10(b). Namely, the polycide film 29 as a material for the control gate electrode, the ONO film, and the polysilicon film 25 as a material for the floating gate electrode are successively removed by etching.
Further, after the resist R22 is removed, a side wall of the polysilicon film 25 as a material for the floating gate electrode is covered with a thermal oxide film 30 as shown in FIGS. 11(a) and 11(b), since the side wall of the polysilicon film 25 is exposed during the patterning of the polycide film 29 for the control gate electrode. Thereafter, as shown in FIGS. 12(a) and 12(b), an impurity is implanted with the control gate electrode used as a mask to form source/drain regions 31, and an interlayer dielectric film 32 is deposited.
According to the above prior art process, the side wall of the polysilicon film as a material for the floating gate must be covered with a thermal oxide film, since the side wall of the polycrystalline film is exposed during the patterning of the polycide film 29 for the control gate electrode. At this time, in the case where the interlayer capacitive film is formed of an ONO film, oxidation to the floating gate electrode and the control gate electrode proceeds from the interface between the first silicon oxide film 26 and the floating gate electrode, and from the interface between the second silicon oxide film 28 and the control gate electrode, respectively. This causes portions 26a and 28a of the ONO film adjacent the exposed side surface of the polysilicon film to be thickened, as shown in FIGS. 11(a) and 11(b).
This partial thickening of the ONO film reduces the ratio (coupling ratio) of the potential difference between the floating gate electrode and the substrate relative to the potential difference between the control gate electrode and the substrate, thereby decreasing the efficiency of performing writing and erasing operations to the floating gate electrode by use of electrons.
Further, as shown in FIGS. 11(a) and 11(b), the oxidation proceeds also to the floating gate electrode from the interface between the tunnel dielectric film and the floating gate electrode as well as to the interfaces of the interlayer capacitive film, thereby thickening a portion 24a of the tunnel oxide film adjacent the exposed side surface of the polysilicon film 25.
Therefore, in performing writing/erasing operations by means of an FN current, the electric field strength between the floating gate electrode and the diffusion layers (source/drain) decreases due to the partial thickening of the tunnel dielectric film, whereby the FN current decreases and the writing/erasing efficiency is lowered.
In order to solve this problem, Japanese Unexamined Patent Publication (Kokai) No. HEI 6(1994)-77493 provides that a side wall of nitride film is formed on a side surface of the gate electrodes. However, this is accompanied by a drawback that the process is complicated, and moreover it is not suited for size reduction of the memory cells because the side wall of nitride film protrudes over the source/drain regions. Also, since the side surface of the gate electrodes must be covered with a highly dielectric thermal oxide film before the side wall of nitride film is formed, it is not possible to prevent creation of a bird's beak in forming the thermal oxide film.
Further, Japanese Unexamined Patent Publication (Kokai) HEI 5(1993)-267684 proposes an NONO film. However, this is accompanied by a drawback that, since the control gate electrode is in contact with the oxide film, oxidation proceeds to the control gate electrode, creating a bird's beak.